• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
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  • 优先权
    • 专利摘要:
    The invention relates to a driver circuit for operating a load (3), preferably at least one light source, in particular an LED, comprising: a first clocked converter (1) with at least one switch (S3) clocked by a control unit (4), the first converter (1) a regulated DC voltage (UBus) is generated at its output; at least one second clocked converter (2) supplied from the regulated DC voltage, from whose output the load (3) can be supplied; wherein the control unit (4) is designed to change the timing of the switch (S3) of the first converter (1} cyclically such that - even if the input voltage of the first converter (1) and the load (3) are constant - a Residual ripple in the regulated DC voltage (UBus) is present; and this residual ripple in the regulated DC voltage (UBus) can be reduced by means of the second converter (2). The invention further relates to an operating device for lighting means and a method for operating lighting means by means of the driver circuit.
    公开号:AT16905U1
    申请号:TGM399/2015U
    申请日:2015-12-22
    公开日:2020-11-15
    发明作者:Netzer Harald
    申请人:Tridonic Gmbh & Co Kg；
    IPC主号:
    专利说明:

    description
    SWITCHING CONVERTER WITH CYCLICAL FREQUENCY CHANGE
    The invention relates to a driver circuit for operating a load, preferably at least one lighting means, in particular an LED. The invention also relates to a corresponding operating device and a method for operating the load.
    In particular, the invention relates to a multi-stage driver circuit consisting of sequentially connected clocked converters, the clocking of a first clocked converter is changed cyclically in order to generate a varying clocking in a subsequent second switching converter.
    In particular, the present invention relates to the operation of light sources, such as LED or OLED as a load.
    In principle, it is already known to supply an LED path, which can have one or more LEDs connected in series, with electrical power starting from an operating device by means of a constant current source. It is also known that the operating device includes a resonance switching converter, for example in the form of an LLC converter, to generate this electrical power.
    The problem is that a regulated DC voltage, for example a bus voltage of a first clocked converter, is very constant, especially when there are low loads on the driver circuit of the operating device. Therefore, the operating frequency of the downstream second switching converter is also very constant. In particular, this constant operating frequency of the downstream second converter is problematic with regard to electromagnetic compatibility, or EMC for short. The constant operating frequency of a half-bridge circuit of the second switching converter and its harmonics of this constant operating frequency prevent the operating device from being able to be operated within permissible standards for LED operation.
    For example, it is known from WO 2014/100844 A2 to specifically interfere with the operating frequency of a resonance switching converter resulting from regulation. A clock change is used in a so-called sweep mode in the LLC resonance converter.
    To improve the EMC characteristics of such driver circuits, this sweep mode of the half-bridge circuit of the resonant switching converter could be used. Operating the resonance switching converter in sweep mode, however, leads to audible noise or visible light flickering, both of which are undesirable.
    It is therefore the object of the present invention to provide a driver circuit whose EMC compatibility is improved without the driver circuit causing an impairment, such as audible noise or visible light flickering, of the connected load.
    [0009] This object is achieved with the features described in the independent claims. Preferred configurations are described in the respective dependent claims.
    In a first aspect of the invention, a driver circuit for operating a load, preferably at least one lighting means, in particular an LED, is provided. The driver circuit has a first clocked converter with at least one switch clocked by a control unit, the first converter generating a regulated DC voltage at its output. The driver circuit also has at least one second clocked converter supplied from the regulated DC voltage, the load being able to be supplied from its output. The control unit is designed to change the timing of the switch of the first converter cyclically in such a way that even if the input voltage of the first converter and the load are constant, there is a residual ripple in the regulated DC voltage.
    and this residual ripple of the regulated DC voltage can be reduced by means of the second converter.
    A central idea of the invention is therefore a deliberate cyclical change in the timing, for example the operating frequency or the switch-on time, of the first switching converter. This cyclical change in the clocking of the switch of the first converter is designed in such a way that it has to be reduced in a switching converter following the first switching converter, and in the ideal case it is even regulated. In this way, the load will be supplied with constant electrical parameters, but the artificially created residual ripple means that the EMC characteristics of the driver circuit are significantly improved.
    In order to achieve this consciously induced change in the timing of the switch of the second switching converter, the timing of the switch of the first converter is therefore varied cyclically - that is, within the scope of a periodically recurring change. As a result of this cyclical variation, the regulated DC voltage is also changed cyclically by means of residual waves. As a result of this residual ripple, the second switching converter has to vary its timing in order to compensate for the residual ripple in the regulated DC voltage.
    As residual ripple, English ripple, a ripple current or a ripple voltage is understood below, which is created by the rectification of an alternating voltage. If a direct voltage is to be created from a sinusoidal alternating voltage through rectification, a mixed voltage always arises from direct and superimposed alternating voltage. The fact that an alternating voltage component still remains despite smoothing is referred to as residual ripple. According to the invention, the residual ripple is deliberately provoked in order to improve the EMC characteristics of a subsequent converter stage.
    The deliberate residual ripple arises accordingly when the load is constant and when the input voltage is constant, so that the properties of the first converter are deliberately impaired.
    The input voltage is preferably an AC mains voltage, for example 230V, or an already rectified voltage. The regulated DC voltage generated by means of the first switching converter is, for example, the bus voltage in a lighting system, also referred to as the intermediate voltage in the driver circuit.
    The second clocked switching converter is connected downstream of the first clocked switching converter. The regulated DC voltage is modulated by the cyclical changing of the clocking, that is to say by deliberately applying changes in the frequency and / or the switch-on time of the switch of the first converter. This regulated DC voltage, which is provided with a residual ripple, is in turn an input voltage of the second clocked converter.
    In order to compensate for the residual ripple by means of the second converter, its clocking must be varied, which results in improved EMC characteristics.
    In a preferred embodiment, the residual ripple can be reduced by cyclically changing the timing of a switch of the second converter. The operating frequency or at least the switch-on time of the switch of the second converter will also be varied. Thus, in particular harmonic oscillations of the switching frequency can be compensated out by a forced cyclical change in the frequency of the second converter, and the electromagnetic compatibility of the driver circuit is enormously improved.
    In a preferred embodiment, the second converter is a resonance converter, preferably an LLC resonance converter, which is operated by means of a half-bridge circuit. The half-bridge circuit can be operated with two switches to which a second switching signal can be applied, the second switching signal having a first switching signal component and a switching signal component complementary thereto. Thus, the forced cyclical variation of the clocking of the switches of the second switching converter due to the complementary character of the second switching signal will result in complete cancellation or at least a significant reduction in the power amplitude of the harmonics of the switching frequency of the second converter, whereby
    is improved by the EMC characteristics without audible noise or visible light flickering.
    Due to the residual ripple in the regulated DC voltage, a change in the half-bridge timing is achieved, which brings about the improved EMC compatibility. Since the LLC resonator compensates for this residual ripple of the regulated DC voltage by changing the half-bridge clock, a very constant output voltage is still obtained for operating the lighting means regardless of this.
    In a preferred embodiment, the first converter has a control unit in order to clock the first switch of the first converter by means of a first switching signal. For this purpose, a control signal from the control unit for cyclically changing the clocking of the first switch of the first converter is applied to the control unit. In this way, the cyclical changing of the timing can be controlled. In this way, both the frequency swing of the residual ripple and the amplitude of the residual waves can be set. This setting option for changing the timing ensures that the residual ripple is reliably reduced and, ideally, completely regulated out, with a constant load voltage being able to be tapped off at the output of the driver circuit in any case.
    In a preferred embodiment, a cyclically changing additional value is applied to a nominal value for the control unit by the control signal in order to bring about the cyclic change in the timing of the first switch of the first converter. The loading takes place by adding and / or subtracting in a cyclical manner. The nominal value is, for example, the input voltage or a value proportional to it.
    Alternatively or additionally, an actual variable for the control unit is acted upon by the control signal, a cyclically changing additional value in order to bring about the cyclical change in the timing of the first switch of the first converter. The loading takes place by adding and / or subtracting in a cyclical manner. The actual value is, for example, the output voltage of the first converter or a value proportional to it.
    By cyclically applying additional values to the setpoint or the actual size, the result of the control unit is deliberately falsified, whereby the timing of the first switching signal is changed cyclically.
    Alternatively or additionally, a cyclically changing additional time value is applied to the switch-on time value of the first switching signal by the control signal in order to effect the cyclical change in the timing of the first switch of the first converter.
    The cyclical change in timing is preferably only used when the load has a load value below a predefined threshold value. The load value denotes in particular an ohmic resistance value with which the load can be characterized in the context of an equivalent circuit diagram.
    In particular, low loads are to be described by the driver circuit proposed here, since, particularly at low loads, the first converter stage supplies a highly precise, regulated direct voltage which causes the disadvantageous EMC effects. The artificial residual ripple produced according to the invention reduces this accuracy.
    In a preferred embodiment, the load is at least one LED. The load value of the LED is determined by a dimming value specification, preferably a dimming value below 50 percent, more preferably below 25 percent of the total light output of the at least one LED. This dimming value specification for setting the lighting means is in particular also fed to the control unit. The control signal is thus able to be activated as a function of a preset dimming value.
    Alternatively or additionally, the load is at least one LED, and the load value is determined by a load current measurement and / or a load voltage measurement.
    In a preferred embodiment, the load is at least one LED and the load value is determined by the duration of the switch-on time of the switch of the first converter. In this way
    the low loads can be determined very easily and electromagnetic compatibility can be increased.
    In a preferred embodiment, a varying timing of the second switching signal of the second converter can be set by the residual ripple of the regulated DC voltage.
    Preferably, at least a third clocked converter is connected downstream of the second converter, the third converter operating the load by clocking a switch of the third converter.
    The first converter is preferably a PFC converter or a Buck converter or a FlyBack converter. All of these clocked switching converters can now selectively vary their operating frequency cyclically. In this way, sufficient residual ripple is generated in the regulated DC voltage, and this residual ripple can be very easily reduced by a downstream switching converter in order to obtain constant load power.
    If, for example, the first switching converter is a PFC converter, a control unit is provided to convert an input voltage into a regulated DC voltage. For this purpose, a control loop is provided in the first transducer, which compares an actual variable and a target variable with one another. In order to enable the cyclical change in the timing of the first converter, either the actual size or the target size are changed by applying additional cyclical values. This results in a control algorithm which has the preceding effects.
    The control unit therefore serves to calculate a suitable switch-on time for a switch on the basis of an actual value. However, before a switching signal for the switch in the first switching converter is generated on the basis of the switch-on duration determined by the control unit, the switch-on duration is supplemented by an additional value, that is, either lengthened or shortened. This additional value changes cyclically.
    In a preferred embodiment, the third converter is a step-down converter, also referred to as a step-down converter, step-down regulator, step-down converter or buck converter. In such a buck converter, the output voltage is always less than the amount of the input voltage.
    According to a second aspect of the invention, an operating device for a lighting means is provided which has a driver circuit of the type described above.
    According to a third aspect of the invention, a method for operating at least one lighting means by means of a driver circuit according to the type described above is provided. The method comprises the steps of: converting an input voltage into a regulated DC voltage by means of a first clocked converter using a switch of the converter that is clocked by a control unit; Converting the regulated DC voltage into a load voltage for operating the load by means of at least one second clocked converter using a switch of the second converter that is clocked by the control unit; Cyclical changing of the timing of the switch of the first converter so that even if the input voltage of the converter and the load are constant, there is a residual ripple in the regulated DC voltage; and reducing this residual ripple of the regulated DC voltage by means of the second converter.
    The residual ripple is preferably provided in order to change the operating frequency of the second converter.
    Preferably, a target size and / or an actual size and / or a switch-on time of the switching signal of the first converter is changed cyclically by means of the control signal.
    The cyclical frequency change is preferably only used when the lighting means has a load value below a predefined threshold value.
    In the following, the invention and further embodiments and advantages of the invention will be explained in more detail with reference to figures, the figures merely being exemplary embodiments of the
    describe finding. The same components in the figures are provided with the same reference symbols. The figures are not to be regarded as true to scale; individual elements of the figures can be shown exaggeratedly large or exaggeratedly simplified.
    [0041] They show:
    1 shows a first exemplary embodiment of a driver circuit according to the invention shown as a block diagram;
    [0043] FIG. 2 shows a second exemplary embodiment of a driver circuit according to the invention shown as a block diagram;
    3 shows an embodiment of a first converter for a driver circuit according to the invention;
    4a-c show exemplary signal curves for cyclically changing the frequency according to the invention;
    Fig. 5 shows a first embodiment of a second converter for a driver circuit according to the invention;
    6 shows a second embodiment of a second converter for a driver circuit according to the invention;
    7 shows an exemplary half-bridge circuit for a second converter of a driver circuit according to the invention;
    8 shows a combination of resonance circuit and transformer for a second converter of a driver circuit according to the invention;
    9 shows an embodiment of a third converter for a driver circuit according to the invention;
    10 shows a process flow diagram for a method according to the invention.
    In Fig. 1, a first embodiment of a driver circuit according to the invention is shown. Here, a first converter 1 is connected to an input voltage L, N. The input voltage is shown here as mains voltage, with a live conductor L of the mains voltage and a neutral conductor N of the mains voltage being shown symbolically. At the output of the first converter stage 1, a regulated DC voltage Ugus based on a ground potential GND can be tapped. According to the driver circuit of the invention, the first converter 1 is followed by a second converter 2. The regulated input voltage Ugus In is converted into a load voltage U_aAst or a load current I_ast. At the output of the second converter 2, a load 3 can be connected, which is shown as an ohmic resistor according to FIG. 1.
    A lighting means, for example at least one LED, is provided as the load 3. The load 3 can symbolize an LED path made up of a plurality of LEDs connected in series. Moreover, it is also possible to view a number of LEDs connected in parallel as the load 3.
    According to the invention, the input voltage L, N is converted into a regulated DC voltage Ugus by means of the first converter 1 in such a way that the clocking generated in the first converter stage 1 is changed cyclically by applying a first switching signal Sig to the switch S3 . This cyclical change in the clocking causes a residual ripple which is reduced in the subsequent second converter stage 2 in order to nevertheless provide the load 3 with a constant voltage U_LaAst or a constant current ILast or a constant power P_ast. With residual ripple is meant the cyclical change in amplitude.
    The cyclical change of the clock, for example the operating frequency or the clock ratio of the switching signal Sig by changing the switch-on time ton or the switch-off time tor, the first converter stage 1 leads to a cyclical change in the clocking in the downstream second converter stage 2, which in particular harmonic oscillations the
    Switching frequency in the second converter 2 are compensated. This improves the EMC characteristics of the driver circuit and enables the driver circuit to generate no disruptive audible noise and also no disruptive flickering of the lighting means as load 3.
    The timing of the first converter stage 1 is changed in particular by a control signal PFC which is fed to the first converter 1. This control signal PFC is generated by a control unit 4, for example. The control signal PFC has a direct influence on a control loop within the first converter 1. In particular, an actual size or a target size within the control loop of the converter stage 1 is varied by means of cyclic manipulation, so that a residual ripple is generated on the regulated DC voltage Ugus. This residual ripple will in turn lead to the second converter stage 2 having a changed timing.
    In Fig. 2, a second embodiment of a driver circuit according to the invention is shown. Only the differences between the driver circuit according to FIG. 1 and the driver circuit according to FIG. 2 are described below. According to FIG. 2, a third converter stage 5 is shown, which is arranged between the second converter stage 2 and the load 3. The third converter stage 5 is preferably a buck converter.
    A power factor correction circuit, PFC, is provided as the first converter 1, for example. In general, however, any type of clocked converter can be viewed as switching converter 1. It is thus also possible to provide step-down converters or step-up converters, in particular in the form of fly-back converters or buck converters, as the first converter 1.
    It is provided that the timing of the switching signal Sig of the first converter 1 is varied cyclically in order to consciously generate a residual ripple on the regulated DC voltage Ugus, which leads to the second converter 2 also changing its timing. By changing the timing of the first switching signal Sig cyclically, the timing of the second switching signal HS, LS of the second converter 2 also changes cyclically, with the compensation of interfering influences, in particular harmonic oscillations, etc. being made possible.
    In Fig. 3 an embodiment of a first converter stage 1 for a driver circuit according to the invention is shown in detail. According to FIG. 3, a power factor correction circuit, or PFC for short, is provided as the first converter 1. A mains voltage L, N is applied to the converter 1. This line voltage L, N is rectified by means of a rectifier unit 24. This is followed by an active PFC circuit consisting of a PFC coil L4, a PFC diode D5 and a PFC switch S3. Finally, a Ceus smoothing capacitor is connected in parallel. A rectified voltage Ugus can be tapped off at the output of the first converter 1.
    In Fig. 3, a so-called boost PFC converter 1 is shown. The boost PFC converter 1 has a PFC coil L4. This coil L4 is connected with a first connection to the rectifier 24 and with a second connection to a first connection of the PFC switch S4 and to the anode D5. A second connection of the switch S3 is connected to the ground potential GND. The switch S3 can therefore either short-circuit the second connection of the coil L4 to ground GND or switch it on to the diode D5. The cathode of the diode D5 is connected to the output Ugsus.
    According to the invention it is now provided that the switch S4 is switched by means of a control unit 11. This control unit has a first input in order to connect a nominal value. The setpoint value can be tapped, for example, from the first connection of the coil L4 and is provided to the control unit 11 directly or via a voltage divider.
    The control unit 11 has a second connection in order to connect an actual variable. This actual value is preferably tapped from the cathode of the diode D5 and made available directly to the control unit 11 or via a voltage divider 11.
    A first switching signal Sig is generated by the control unit 11 in order to control the switch S4 on the basis of the values of the target size and the actual size. The switching signal Sig is on
    pulse-width modulated signal, the timing of which is varied cyclically according to the invention by a control signal PFC. In this way, a regulated direct voltage Ugus is obtained, which has a deliberate residual ripple. In particular with low loads 3, for example a dimming value specification of less than 50% of the total light output of a lamp, the driver circuit is thus equipped with improved EMC compatibility.
    The control signal PFC is provided from a control unit 4. The control signal PFC is, in particular, a cyclical manipulation in the context of an additional value that is either added to or subtracted from the actual size or the setpoint size. The result of the control unit 11 is thus intentionally manipulated in order to obtain a cyclical clock modulation. Alternatively, the switch-on time ton prc of the switch S4 can be subjected to cyclical variations by means of the control signal PFC. Such a cyclical change in the switch-on time ton_Pro is shown, for example, in FIG. 4c.
    The output voltage of the PFC converter 1 is a bus voltage Ugus in the form of a DC voltage or an essentially constant voltage. Starting from a 230 volt mains alternating voltage L, N, the bus voltage Ugus can be 400 volts, for example. Due to the mains voltage frequency of 50 Hz applicable in Europe, the bus voltage V.us provided by the PFC circuit 1 usually has a residual ripple with twice the mains frequency, 100 Hz in Europe and 120 Hz in the USA.
    The converter 1 can be, for example, a step-up converter, a flyback converter or an isolated flyback converter. The bus voltage Veus is then fed to a second converter 2. Furthermore, a control unit 11 is provided, which can be implemented in particular as an integrated circuit, such as an ASIC or microprocessor or a hybrid thereof.
    The control unit 11 communicates, for example, via a galvanic decoupling with an interface. This interface has connections for connecting an external analog or digital bus (not shown), which can be designed, for example, in accordance with the DALI industry standard. In this way, data can be transmitted bi-directionally or unidirectionally according to this protocol, for example a dimming specification or a color temperature. Alternatively or additionally, however, unidirectional or bidirectional signals can also be transmitted at this interface in accordance with other standards.
    In FIG. 4a, a first switching signal Sig of the first converter 1 is initially shown. This switching signal Sig is a PWM signal with a switch-on time ton prc, which is determined by the control unit 11.
    4b shows a time curve of a first half cycle of the input signal L in comparison to the cathode current signal Ips katnoae of the diode D5. The curve shows the current profile I_4 through the coil L4 when the PFC is operated in a critical conduction mode, CRM, in which the current through the coil has zero amperes for each switching cycle of the switch S3, in order to achieve the lowest possible loss Ensure switching. The switch-on time ton PFc of the switching signal is the time between a zero point of the current Iı4 and a peak value of the current I.4. The switch-off time tor prc is the time between a peak value of the current Iı4 and a zero point of the current Iı4. The sum of ton Prc UNd tor pFo is the duration T of the switching signal.
    Alternatively and not shown in FIG. 4b, the control unit 11 can be set up to set a non-intermittent operation, English continuous current mode, CCM, or an intermittent operation, English discontinuous current conduction mode, DCM.
    FIG. 4c now shows a curve of a time value of the switch-on time ton prc over time. The Y-axis corresponds to the duration of the switch-on time of switch S3.
    Starting from a standard value ton _norm (shown in dashed lines), the value for the switch-on time ton prc is incremented and decremented in stages. The time interval between the individual steps for incrementing or decrementing is determined by the clock frequency of the
    Converter 1 determined. The incrementing and decrementing is repeated cyclically so that the mean value of the switch-on time ton Prc corresponds to the standard value ton _norm. The incrementing and / or decrementing is carried out by the control unit 11 and provided to the control unit as a control signal PFC.
    The height of all stages is referred to as "sweep amplitude". The residual ripple of the regulated DC voltage can be set by the "sweep amplitude" or by the length of the sweep period Tsweer or the frequency of the cycle Tsweer, so that it can be ensured that the residual ripple can be compensated for by the following converter 2.
    By changing the switching frequency according to the invention - the frequency deviation, for example in the range of a few kilohertz - an EMC reduction in the sense of the EMC regulations can be achieved.
    The previously mentioned 100 Hertz residual ripple at the output of the PFC converter 1 is reduced by the second converter 2. In particular, the amplitude of the residual waves is reduced; in the ideal case, the residual ripple is completely regulated out.
    Thus, according to the present invention, the artificial fixed frequency sweep can be selectively switched on or amplified when a low light output is required at which the fluctuation in the output voltage of the PFC converter 1 does not change by itself the operating frequency of the second converter 2 leads.
    It can thus be provided that this sweep operation is adaptive, i.e. for example, can also be carried out selectively depending on the current dimming value of the LED system. In particular, it can only be carried out if the light output is below a predetermined threshold value.
    If, according to the invention, the PFC converter 1 now provides an output voltage with a residual ripple at a frequency of 100 Hertz, the operating frequency of the second converter 2 is selectively applied with a cyclically changed clock in the range of a few kilohertz. In addition, the frequency deviation is relatively small, so that the fluctuation in the area of the cyclical change in timing is invisible to humans.
    For example, if the time average of the operating frequency of the first transducer 1 is in a range between 80 kHz and 100 kHz, the frequency deviation, i. the symmetrical frequency sweep, lie in a range of a few kilohertz.
    In Fig. 5 a first embodiment of a second converter stage 2 is shown for a driver circuit of the invention. The second converter stage 2 according to FIG. 5 comprises four functional units. First, a half-bridge circuit 21 is provided, to which a regulated input voltage Ugus with artificially generated residual ripples can be applied. The half-bridge circuit 21 has two switches S1, S2 connected in series, which are switched by means of switching signal components HS, LS which are switched in a complementary manner. An alternating voltage signal is thus again obtained at the output of the half-bridge circuit 21, with a direct voltage offset of the level Ubus / 2. The signal toggles between Ubus and Gnd.
    The output voltage of the PFC converter 1 can thus be fed to a half-bridge circuit 21 functioning as an inverter. The control signals HS, LS for clocking the switches S1, S2 can also be generated by the control unit 11.
    The resonance circuit 22 connects between the switches S1, S2 of the half bridge 21. The resonance circuit 22 can be configured as desired and, in the case according to FIG. 5, is configured as a so-called LLC resonance circuit. A first capacitor C1 is connected in series with a first coil L1 and a second coil L2. According to FIG. 5, the second coil L2 is at the same time the primary winding of a transformer T of a downstream transformer stage 23. This transformer 23 serves to galvanically separate the load 3 from the regulated DC voltage Ugus. The secondary winding L3 of the transformer stage 23 is in turn connected to a rectifier circuit 24. According to FIG. 5, the rectifier circuit 24 consists of four diodes D1, D2, D3 and D4, which are connected as a Graetz circuit to provide a full bridge
    Form rectifier. A constantly regulated voltage ULaAst or a constantly regulated current I_ast can be tapped off at the output of the rectifier 24.
    If a residual ripple is now imposed on the regulated DC voltage Ugus by means of the control signal PFC, the second converter stage 2 is consciously forced to vary its operating frequency by applying the corresponding switching signal components HS, LS in order to improve the EMC characteristics.
    6 shows a second embodiment of a second converter 2 for a driver circuit according to the invention. Only the differences between the converter 2 according to FIG. 5 and the second converter 2 according to FIG. 6 are explained in more detail below. In contrast to FIG. 5, the rectifier 24 is alternatively designed in that the secondary winding L3 of the transformer stage 23 has a center tap and two diodes D1 and D2.
    FIG. 7 shows an example of an improved half-bridge circuit 21 for a second converter 2 of a driver circuit according to the invention. The half-bridge circuit 21 has two field effect transistors Q1, Q2 as switches S1, S2, which are connected in series. A switching signal component HS is connected to the gate connection of the field effect transistor Q1. A second switching signal component LS, which is complementary to the switching signal component HS, is connected to the gate connection of the field effect transistor Q2. In order to reduce switching capacitances, compensation capacitors Ca are connected between the respective drain and source connections of the field effect transistors Q1, Q2. A half-bridge circuit 21 of this type enables the edges of the half-bridge midpoint voltage to become flatter, which leads to an improvement in the EMI spectrum.
    In Fig. 8, an alternative combination of resonance circuit 22 and transformer 23 is shown. In contrast to the variants shown in FIG. 5 and FIG. 6, the primary coil L2 ′ of the transformer 23 is shown here separately from the second coil L2 of the resonance circuit 22. This enables an improved setting of the resonance circuit 22 by means of the coils L1 and L2. The transformer 23 according to FIG. 8 is preferably designed as an ideal transformer T.
    The following structure is preferably used. The coils L1 and L2 are integrated in the transformer T, L1 is the leakage inductance from the transformer T and L2 is the magnetizing inductance. In this way, only one component is used in which L1 and L2 are formed together. Alternatively and also preferably, the coil L1 is connected in series with the primary winding of the transformer T as an additional, external inductance, so that two components are used, the inductance L1 and the primary winding L2 'of the transformer T.
    FIG. 9 shows an exemplary third converter 5 of a driver circuit according to the invention according to FIG. 2. An output signal of the second converter stage 2 is connected to the input of the third converter stage 5. By means of a buck converter, consisting of a buck switch S4, a buck coil L5 and a buck diode D6, the input voltage of the third converter 5 can now be converted into the load voltage U_Last or the load current I_ası. A charging capacitor Ceuc «makes it possible to prevent further ripples, so that a very constant output voltage U_ast or a highly constant current I_Ast can be set.
    10 shows a process flow diagram for a method 100 according to the invention. In step 101, an input voltage L, N is converted into a regulated direct voltage Ugus by means of a first clocked converter 1. According to step 102, the regulated direct voltage Ugus is converted into a load voltage ULAst by means of at least a second clocked converter 2. In step 103 by cyclically changing the timing of the first switch S3 of the first converter 1, a residual ripple on the regulated DC voltage Ugus is obtained. In the following step 104, the residual ripple is reduced by the second converter 2.
    All of the features described, shown and / or claimed can be combined with one another as desired.
    REFERENCE MARK
    1 First converter, boost PFC converter 11 Control unit 2 Second converter, LLC converter
    21 half bridge
    22 Resonant circuit 23 Transformer 24 Equalizer
    3 load
    4 control unit
    5 Third converter, buck converter
    BUCK Third switching signal
    C1, Cr resonance capacitor
    CBuck charging capacitor buck converter
    Cout charging capacitor rectifier
    Cprc charging capacitor PFC converter
    Ca compensation capacitor
    D1-D4 rectifier diodes
    D5 PFC diode
    D6 buck diode
    Gnd ground potential, ground
    HS First switching signal component of the half bridge Iload load current
    L Live conductor of the mains voltage L1, Lr First resonance coil
    L2, Lm Second resonance coil
    L2 'First transformer winding
    L3, L3a Second transformer winding
    L3b Third transformer winding
    L4 PFC coil
    L5 buck coil
    LS Second switching signal component of the half bridge N Neutral conductor of the mains voltage
    PFC control signal of the first converter
    S1, Q1 First switch of the half bridge
    S2, Q2 Second switch of the half bridge
    S3 switch of the first converter Ss4 switch of the third converter Sig First switching signal
    Ton_add additional time value
    ton_PFC On-time PFC switch
    Tsweep Period of the cyclical change in UBus bus voltage
    ULload load voltage
    Usweep sweep amplitude
    权利要求:
    Claims (10)
    [1]
    1. Driver circuit for operating a load (3), preferably at least one light source, in particular an LED, comprising: a first clocked converter (1) with at least one switch (S3) clocked by a control unit (4), the first converter (1 ) a regulated DC voltage (Ugus) is generated at its output; at least one second clocked converter (2) supplied from the regulated DC voltage, from whose output the load (3) can be supplied; wherein the control unit (4) is designed to change the timing of the switch (S3) of the first converter (1) cyclically in such a way that - even if the input voltage of the first converter (1) and the load (3) are constant - a There is residual ripple in the regulated DC voltage (Ugus); and this residual ripple of the regulated direct voltage (Ugus) can be reduced by means of the second converter (2).
    [2]
    2. Driver circuit according to claim 1, wherein the residual ripple can be reduced by cyclically changing the timing of a switch (S1, S2) of the second converter (2).
    [3]
    3. Driver circuit according to one of the preceding claims, wherein the second converter (2) is a resonance converter, preferably an LLC resonance converter, which is operated by means of a half-bridge circuit (21); and wherein the half-bridge circuit (21) is operated with two switches (S1, S2) to which a second switching signal (HS, LS) can be applied, the second switching signal (HS, LS) having a first switching signal component (HS) and a complementary one Has switching signal component (LS).
    [4]
    4. Driver circuit according to one of the preceding claims, wherein the first converter (1) has a control unit (11) to clock the first switch (S3) of the first converter (1) by means of a first switching signal (Sig); and a control signal (PFC) from the control unit (4) for cyclically changing the timing of the first switch (S3) of the first converter (1) is applied to the regulating unit (11).
    [5]
    5. Driver circuit according to claim 4, wherein a cyclically changing additional value is applied to a nominal value (nominal) for the control unit (11) by the control signal (PFC) in order to reflect the cyclic change in the timing of the first switch (S3) of the first converter (1) to effect.
    [6]
    6. Driver circuit according to claim 4 or 5, wherein an actual variable (actual) for the control unit (11) by the control signal (PFC) a cyclically changing additional value is applied to the cyclical change in the timing of the first switch (S3) of the first converter (1) to effect.
    [7]
    7. Driver circuit according to one of claims 4 to 6, wherein the switch-on time value (Ton) of the first switching signal (Sig) by the control signal (PFC) a cyclically changing additional time value (taaa) is applied to the cyclical change in the timing of the first switch ( S3) of the first converter (1).
    [8]
    8. Driver circuit according to one of the preceding claims, wherein the cyclical change in the timing is only used when the load (3) has a load value below a predefined threshold value.
    [9]
    9. Operating device for a lamp comprising a driver circuit according to one of the preceding claims.
    [10]
    10. The method (100) for operating a load (3), preferably at least one lighting means, in particular an LED, by means of a driver circuit according to one of claims 1 to 8, with the method steps:
    Converting (101) an input voltage (L, N) into a regulated DC voltage (Ugus)
    by means of a first clocked converter (1) using a switch (S3) of the converter (1) clocked by a control unit (4);
    Converting (102) the regulated DC voltage (Ugus) into a load voltage (Urast) for operating the load (3) by means of at least one second clocked converter (2) using a switch (S1, S2) of the second that is clocked by the control unit (4) Converter (2);
    Cyclical changing (103) of the timing of the switch (S3) of the first converter (1), so that even if the input voltage (L, N) of the converter (1) and the load (3) are constant, there is a residual ripple in the regulated DC voltage ( Ugus) is present; and
    Reducing (104) this residual ripple of the regulated direct voltage (Ugus) by means of the second converter (2).
    In addition 9 sheets of drawings
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20020196006A1|2001-06-21|2002-12-26|Champion Microelectronic Corp.|Volt-second balanced PFCPWM power converter|
    US20120112657A1|2009-07-03|2012-05-10|Koninklijke Philips Electronics N.V.|Low cost power supply circuit and method|
    US20140160805A1|2012-12-07|2014-06-12|Apple Inc.|Hysteretic-mode pulse frequency modulated resonant ac to dc converter|
    US20150091458A1|2013-10-01|2015-04-02|General Electric Company|Two-stage ac-dc power converter with selectable dual output current|
    DE102010039154A1|2010-08-10|2012-02-16|Tridonic Gmbh & Co. Kg|Modulation of a PFC in DC mode|
    CN104885566B|2012-12-28|2018-01-02|赤多尼科两合股份有限公司|The operation of light-emitting device with resonance converter|DE102020206519A1|2020-05-26|2021-12-02|Robert Bosch Gesellschaft mit beschränkter Haftung|Battery system and method of operating the battery system|
    法律状态:
    优先权:
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    DE102015223589.0A|DE102015223589A1|2015-11-27|2015-11-27|Switching converter with cyclic frequency change|
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